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Freescale Semiconductor /MK70F15WS /PTA /PDDR

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Interpret as PDDR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)PDD

PDD=0

Description

Port Data Direction Register

Fields

PDD

Port data direction

0 (0): Pin is configured as general-purpose input, for the GPIO function.

1 (1): Pin is configured for general-purpose output, for the GPIO function.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data